Semester 3Year 2 · OddCore Subject★★★ Moderate
CS 202

Computer Organization and Architecture

Computer hardware fundamentals, CPU design, memory hierarchy, and I/O systems.

3Units
12Topics
4Credits
60hLecture hrs
100Max marks
Your Progress
0 / 12 topics
0% complete
Overview
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Why it matters
Understanding how CPUs execute instructions, how cache works, how pipelining speeds up processing — this explains WHY your code is fast or slow. Essential for performance optimization and systems programming.
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Placement relevance
Core companies (Intel, AMD, Qualcomm, NVIDIA) directly test this. For software roles, understanding CPU architecture helps in writing optimized code. GATE CSE has high weightage (12-15 marks).
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Prerequisites for
Operating Systems · Compiler Design · Embedded Systems · VLSI Design · Computer Networks · Parallel Computing
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Recommended books
Computer Organization and Architecture by William Stallings · Computer System Architecture by M. Morris Mano · Computer Organization by Carl Hamacher · Computer Architecture: A Quantitative Approach by Hennessy & Patterson
Curriculum — 3 Units
U1
Unit 1 · 4 Topics · 0% complete
Digital Logic
⚡ Key Formulae
Boolean Laws:A + A' = 1; A · A' = 0; De Morgan's: (A+B)' = A'·B'
K-Map:Group 1s in powers of 2 (1,2,4,8) to minimize SOP
Flip-Flops:SR, JK, D, T flip-flops; D: Q(t+1) = D; T: Q(t+1) = T⊕Q
Boolean Algebra
Logic Gates
Combinational Circuits
Sequential Circuits
U2
Unit 2 · 4 Topics · 0% complete
CPU Architecture
⚡ Key Formulae
CPU Time:CPU Time = Instructions × CPI × Clock Period
Speedup:Speedup = Time(without) / Time(with); Ideal pipeline speedup = n stages
Cache Hit Ratio:Avg Access Time = Hit% × Cache Time + Miss% × (Cache + Memory)
MIPS:MIPS = Instruction Count / (Execution Time × 10⁶)
Instruction Set
Addressing Modes
Pipelining
Cache Memory
U3
Unit 3 · 4 Topics · 0% complete
Memory Hierarchy
⚡ Key Formulae
Cache Size:Total Size = 2^s × 2^b × (2^t + valid + dirty)
Page Table Entry:Virtual Address = Page Number + Page Offset
Cache Organization
Virtual Memory
Memory Mapping
Page Replacement
Previous Year Questions
Unit 22023 · End Semester10 marks
A 5-stage pipeline has stages: IF, ID, EX, MEM, WB with times 1ns, 2ns, 2ns, 1ns, 1ns. Calculate: a) Clock period, b) Execution time for 100 instructions without and with pipelining, c) Speedup achieved.
Unit 12023 · Mid Semester8 marks
Design a full adder circuit using half adders. Draw logic diagram and truth table. Derive Boolean expressions for Sum and Carry.
Unit 22022 · End Semester10 marks
A cache has 64 blocks with block size 16 bytes. Main memory has 4096 blocks. For direct mapping, find: a) Tag bits, b) Index bits, c) Offset bits, d) Total cache size.
Exam Strategy
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Numerical problems = 50% marks
Cache calculations, pipeline speedup, CPI, MIPS, memory address mapping — practice at least 20 numerical problems. Show all steps even if answer is wrong.
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Draw circuit diagrams
Logic gates, flip-flops, ALU, cache structure — diagrams earn marks even if explanation is incomplete. Use proper symbols for gates (AND, OR, NOT, XOR).
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Understand, don't memorize
Why does pipelining speed up? How does cache reduce access time? Examiners ask 'Explain the concept' — rote learning doesn't work here.
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Timing diagrams for sequential circuits
Flip-flop questions need timing diagrams showing CLK, inputs, outputs. Practice drawing waveforms for SR, JK, D, T flip-flops.
Related Subjects
Semester 3
Digital Electronics
EC 201
Semester 4
Operating Systems
CS 402
Semester 6
Microprocessors
CS 601